Using Genetic Algorithms for Subset Selection for Partial Fault Tolerance in Reconfigurable Logic

As field programmable gate arrays and other reconfigurable logic devices are increasingly used for aerospace and terrestrial applications, fault tolerance methodologies have been developed to improve reliability. Applying fault tolerance to an entire design may incur prohibitive area and energy penalties, and a need exists for techniques that can trade fault tolerance for lower area penalties. However, selecting a circuit subset that minimizes both the area overhead and the vulnerability to faults remains an open topic. Area-Constrained Partial Fault Tolerance (ACPFT) is a unique approach that explicitly accepts the device resources as an input and attempts to find a maximally fault-tolerant subset within this constraint. While previous options in ACPFT determined this subset from different heuristics, this paper presents an extension called ACPFT-GA that uses genetic algorithms for subset selection. Testing shows an improvement of up to 31.92% more coverage than the previous version.