An ASIC Design of a Novel Pipelined and Parallel Sorting Accelerator for a Multiprocessor-on-a-chip

Nozar Tabrizi; Nader Bagherzadeh

An ASIC Design of a Novel Pipelined and Parallel Sorting Accelerator for a Multiprocessor-on-a-chip

Kettering University

Research output: Contribution to journal › Article › peer-review

Abstract

We introduce a pipelined and parallel sorting algorithm, with the time, logic, and memory complexity of O(n), O(radicn) and O(n), respectively. We then model, verify, and synthesize this unconditional algorithm for 4k-word clusters as an ASIC accelerating, plug-in engine tailored to MaRS, a multiprocessor-on-a-chip that we have recently developed; so that this engine may replace any of the processing elements (PEs) in MaRS, and provide the other PEs with an efficient sort function, using the same network protocol based on which inter-PE communication is carried out

Original language	American English
Journal	IEEE Xplore
State	Published - Apr 3 2006

Keywords

Application specific integrated circuits
Sorting
Mars
Engines
Clustering algorithms
Network synthesis
Protocols
Communication channels
Logic
Acceleration

Disciplines

Electrical and Computer Engineering

Access to Document

https://doi.org/10.1109/ICASIC.2005.1611246

Cite this

@article{0410a20144f14247a9a9647cc274c97b,

title = "An ASIC Design of a Novel Pipelined and Parallel Sorting Accelerator for a Multiprocessor-on-a-chip",

abstract = " We introduce a pipelined and parallel sorting algorithm, with the time, logic, and memory complexity of O(n), O(radicn) and O(n), respectively. We then model, verify, and synthesize this unconditional algorithm for 4k-word clusters as an ASIC accelerating, plug-in engine tailored to MaRS, a multiprocessor-on-a-chip that we have recently developed; so that this engine may replace any of the processing elements (PEs) in MaRS, and provide the other PEs with an efficient sort function, using the same network protocol based on which inter-PE communication is carried out",

keywords = "Application specific integrated circuits, Sorting, Mars, Engines, Clustering algorithms, Network synthesis, Protocols, Communication channels, Logic, Acceleration",

author = "Nozar Tabrizi and Nader Bagherzadeh",

year = "2006",

month = apr,

day = "3",

language = "American English",

journal = "IEEE Xplore",

}

TY - JOUR

T1 - An ASIC Design of a Novel Pipelined and Parallel Sorting Accelerator for a Multiprocessor-on-a-chip

AU - Tabrizi, Nozar

AU - Bagherzadeh, Nader

PY - 2006/4/3

Y1 - 2006/4/3

N2 - We introduce a pipelined and parallel sorting algorithm, with the time, logic, and memory complexity of O(n), O(radicn) and O(n), respectively. We then model, verify, and synthesize this unconditional algorithm for 4k-word clusters as an ASIC accelerating, plug-in engine tailored to MaRS, a multiprocessor-on-a-chip that we have recently developed; so that this engine may replace any of the processing elements (PEs) in MaRS, and provide the other PEs with an efficient sort function, using the same network protocol based on which inter-PE communication is carried out

AB - We introduce a pipelined and parallel sorting algorithm, with the time, logic, and memory complexity of O(n), O(radicn) and O(n), respectively. We then model, verify, and synthesize this unconditional algorithm for 4k-word clusters as an ASIC accelerating, plug-in engine tailored to MaRS, a multiprocessor-on-a-chip that we have recently developed; so that this engine may replace any of the processing elements (PEs) in MaRS, and provide the other PEs with an efficient sort function, using the same network protocol based on which inter-PE communication is carried out

KW - Application specific integrated circuits

KW - Sorting

KW - Mars

KW - Engines

KW - Clustering algorithms

KW - Network synthesis

KW - Protocols

KW - Communication channels

KW - Logic

KW - Acceleration

UR - https://digitalcommons.kettering.edu/electricalcomp_eng_conference/17

UR - https://doi.org/10.1109/ICASIC.2005.1611246

M3 - Article

JO - IEEE Xplore

JF - IEEE Xplore

ER -

An ASIC Design of a Novel Pipelined and Parallel Sorting Accelerator for a Multiprocessor-on-a-chip

Abstract

Keywords

Disciplines

Access to Document

Other files and links

Cite this