A Parallel Sort Engine with Dynamic Memory for a Multiprocessor-on-a-Chip

Nozar Tabrizi; Nader Bagherzadeh

A Parallel Sort Engine with Dynamic Memory for a Multiprocessor-on-a-Chip

Kettering University

Research output: Contribution to conference › Presentation

Abstract

We propose a custom-designe d alternative to a memory system (generated by a memory generator) used in a 4K-word sorting accelerator which improves area efficiency by some 20%. We also show how the control unit is dramatically simplified with this n ew memory comparing with the sophisticated memory controller in the previous version. Furthermore, s ince the memory introduced here is custom designed, its size is tailored to any specific need.

Original language	American English
State	Published - Nov 22 2006
Event	Proceedings of the Fourth IASTED International Conference on Circuits, Signals, and Systems (CSS) 2006 - Duration: Nov 22 2006 → …

Conference

Conference	Proceedings of the Fourth IASTED International Conference on Circuits, Signals, and Systems (CSS) 2006
Period	11/22/06 → …

Keywords

ASIC design
Dynamic memory cells
Network-on-a-chip
Sorting accelerator
VLSI

Disciplines

Electrical and Computer Engineering

Access to Document

https://www.actapress.com/Content_Of_Proceeding.aspx?ProceedingID=419

Cite this

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title = "A Parallel Sort Engine with Dynamic Memory for a Multiprocessor-on-a-Chip",

abstract = " We propose a custom-designe d alternative to a memory system (generated by a memory generator) used in a 4K-word sorting accelerator which improves area efficiency by some 20%. We also show how the control unit is dramatically simplified with this n ew memory comparing with the sophisticated memory controller in the previous version. Furthermore, s ince the memory introduced here is custom designed, its size is tailored to any specific need.",

keywords = "ASIC design, Dynamic memory cells, Network-on-a-chip, Sorting accelerator, VLSI",

author = "Nozar Tabrizi and Nader Bagherzadeh",

year = "2006",

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note = "Proceedings of the Fourth IASTED International Conference on Circuits, Signals, and Systems (CSS) 2006 ; Conference date: 22-11-2006",

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AU - Bagherzadeh, Nader

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N2 - We propose a custom-designe d alternative to a memory system (generated by a memory generator) used in a 4K-word sorting accelerator which improves area efficiency by some 20%. We also show how the control unit is dramatically simplified with this n ew memory comparing with the sophisticated memory controller in the previous version. Furthermore, s ince the memory introduced here is custom designed, its size is tailored to any specific need.

AB - We propose a custom-designe d alternative to a memory system (generated by a memory generator) used in a 4K-word sorting accelerator which improves area efficiency by some 20%. We also show how the control unit is dramatically simplified with this n ew memory comparing with the sophisticated memory controller in the previous version. Furthermore, s ince the memory introduced here is custom designed, its size is tailored to any specific need.

KW - ASIC design

KW - Dynamic memory cells

KW - Network-on-a-chip

KW - Sorting accelerator

KW - VLSI

UR - https://digitalcommons.kettering.edu/electricalcomp_eng_facultypubs/14

UR - https://www.actapress.com/Content_Of_Proceeding.aspx?ProceedingID=419

M3 - Presentation

T2 - Proceedings of the Fourth IASTED International Conference on Circuits, Signals, and Systems (CSS) 2006

Y2 - 22 November 2006

ER -

A Parallel Sort Engine with Dynamic Memory for a Multiprocessor-on-a-Chip

Abstract

Conference

Keywords

Disciplines

Access to Document

Other files and links

Cite this